Voltage level shifters are well-known and described for example in U.S. Pat. No. 7,541,837, U.S. Pat. No. 7,501,856 and U.S. Pat. No. 7,567,112. Voltage level shifters serve to translate a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence, with different high/low voltages for the output signal and for the input signal, respectively. The input signal is provided by an input voltage varying between a first input voltage level and a second input voltage level. The output signal is provided by an output voltage varying between a first output voltage level and a second output voltage level, of which at least one is different from the corresponding input voltage level.
Quite generally, the requirement for high frequency and low power of processors, notably for mobile products, often results in complex power management schemes with mixing power domains, supplied by different power supply voltages. A level shifter can be a critical cell, as it participates in timing the critical path. Although in many high performance conditions, voltage levels are usually fairly close and a level shifter may not be required in these conditions, the level shifter is often still included with an impact on the overall delay.
Schematically shown in FIG. 1 is an example of a conventional differential voltage level shifter 1. Level shifter 1 comprises an input port 12 for receiving an input signal IN_L, an output port 14 for delivering a corresponding output signal OUT_H, a node 16, supply voltage providers 18 and 20, PMOS transistors 22 and 26, NMOS transistors 24 and 28, and an inverter 30. PMOS 22 and NMOS 24 form a first pull-up-pull-down-stage 22, 24. PMOS 26 and NMOS 28 form a second pull-up-pull-down-stage 26, 28. Each of the first pull-up-pull-down stage and the second pull-up-pull down stage has a first state and a second state and is arranged to deliver the first output voltage level VBB when in its first state and the second output voltage level VPP when in its second state. The first pull-up-pull-down stage and the second pull-up-pull-down stage are cross-coupled. Any one of the first pull-up-pull-down stage and the second pull-up-pull-down stage assuming its first state favors the respective other one of the first pull-up-pull down stage and the second pull-up-pull-down stage to assume its second state. Similarly, any one of the first pull-up-pull-down stage and the second pull-up-pull-down stage assuming its second state favors the respective other one of the first pull-up-pull-down stage and the second pull-up-pull-down stage to assume its first state.
The input signal IN_L is provided by an input voltage VIN which varies between a first input voltage level VSS (low) and a second input voltage level VDD (high). The output signal OUT_H is provided by an output voltage VOUT which varies between the first output voltage level VBB and the second output voltage level VPP. The binary input signal IN_L represents a binary sequence, and the above mentioned components are coupled to each other in such a manner as to translate the binary input signal IN_L to the binary output signal OUT_H so that both signals represent the same binary sequence, but with the high-low voltage difference being higher (or lower) at the output side than at the input side. The input voltage VIN assuming the first input voltage level VSS causes the first pull-up-pull-down stage 22, 24 to assume its second state and the second pull-up-pull-down stage 26, 28 to assume its first state, whereas the input voltage VIN assuming the second input voltage level (VDD) causes the first pull-up-pull-down stage 22, 24 to assume its first state and the second pull-up-pull-down stage 26, 28 to assume its second state.
More specifically, the level shifter 1 operates as follows. When input voltage VIN is at voltage level VSS (low), NMOS 24 and PMOS 26 are conductive (open) whereas NMOS 28 and PMOS 22 are non-conductive (closed), and the output voltage VOUT which is present at node 16 and at output port 14 is at voltage level VPP (high). In contrast, when the input voltage VIN assumes the voltage level VDD (high), NMOS 28 and PMOS 22 are open while NMOS 24 and PMOS 26 are closed, and the output voltage VOUT assumes the voltage level VBB (low).
The double-stage structure formed of first stage 22, 24 and second stage 26, 28 effectively suppresses leakage currents between the VBB-VPP voltage domain (on the input side) and the VSS-VDD voltage domain (on the output side). On the other hand, it involves a fairly important propagation delay, i.e. a time delay between the output signal OUT_H relative to the input signal IN_L. A leakage current in this context is an electric current that persists when the output voltage VOUT has assumed one of its stationary levels (VBB and VPP). Quite generally, a trade-off often needs to be made between leakage currents and the propagation delay.